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PS_Method_CCS_test
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PS_Method_CC...
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Armadillo_example
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link.cmd

link.cmd 1.5 KB
Histórico Raw

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  1. //-heap  0x1000000
    2. 

  2. -heap  0x600000
    3. 

  3. -stack 0x600000
    4. 

  4. 

  5. MEMORY
    6. 

  6. {
    7. 

  7. 	/* Local L2, 0.5~1MB*/
    8. 

  8. 	VECTORS: 	o = 0x00800000  l = 0x00000200
    9. 

  9. 	LL2_RW_DATA: 	o = 0x00800200  l = 0x0003FE00
    10. 

  10. 

  11. 	/* Shared L2 2~4MB*/
    12. 

  12. 	SL2: 		o = 0x0C000000  l = 0x003fffff
    13. 

  13. 

  14. 	/* External DDR3, upto 2GB per core */
    15. 

  15. 	DDR3_CODE: 	o = 0x80000000  l = 0x01000000   /*set memory protection attribitue as execution only*/
    16. 

  16. 	DDR3_R_DATA: 	o = 0x81000000  l = 0x01000000 	 /*set memory protection attribitue as read only*/
    17. 

  17. 	DDR3_RW_DATA: 	o = 0x82000000  l = 0x20000000   /*set memory protection attribitue as read/write*/
    18. 

  18. }
    19. 

  19. 

  20. SECTIONS
    21. 

  21. {
    22. 

  22. 	vecs       	>    VECTORS
    23. 

  23. 

  24. 	.text           >    DDR3_RW_DATA
    25. 

  25. 	.cinit          >    LL2_RW_DATA
    26. 

  26. 	.const          >    LL2_RW_DATA
    27. 

  27. 	.switch         >    LL2_RW_DATA
    28. 

  28. 

  29. 

  30. 	/*.stack          >    SL2*/
    31. 

  31. 

  32. 	.stack          >  DDR3_RW_DATA
    33. 

  33. 

  34. 	GROUP
    35. 

  35. 	{
    36. 

  36. 		.neardata
    37. 

  37. 		.rodata
    38. 

  38. 		.bss
    39. 

  39. 	} 		>    LL2_RW_DATA
    40. 

  40. 	.far            >    LL2_RW_DATA
    41. 

  41. 	.fardata        >    LL2_RW_DATA
    42. 

  42. 	.cio            >    LL2_RW_DATA
    43. 

  43. 	.sysmem         >    DDR3_RW_DATA
    44. 

  44. /*	QMSS_Data:linkingRAM1 		> 	DDR3_RW_DATA
    45. 

  45. 	QMSS_Data:Descriptor_SL2 	> 	DDR3_RW_DATA
    46. 

  46. 	PacketData:buffer_SL2 		> 	DDR3_RW_DATA
    47. 

  47. 	QMSS_Data:Descriptor_LL2 	> 	DDR3_RW_DATA
    48. 

  48. 	PacketData:buffer_LL2 		> 	DDR3_RW_DATA
    49. 

  49. 	QMSS_Data:Descriptor_DDR 	> 	DDR3_RW_DATA
    50. 

  50. 	PacketData:buffer_DDR 		> 	DDR3_RW_DATA*/
    51. 

  51. 	.c6xabi.extab				>	LL2_RW_DATA
    52. 

  52. 	.c6xabi.exidx				>	LL2_RW_DATA
    53. 

  53. 	.init_array				    >	LL2_RW_DATA
    54. 

  54. /*	SL2Mem						>	SL2
    55. 

  55. 	.SL2						>	SL2
    56. 

  56. 	.flag_buf                   >	DDR3_RW_DATA*/
    57. 

  57. }
    58. 

  58. 

  59.